I've been converting my monitor/cold start loader for CPM from my old home made assembly language to ASM. In the process I found some old bugs that I repaired and I wanted to improve my Wait Interrupt routine for CPM. I found something that confuses me.
My new Wait Interrupt routine
1. Waits for the interrupt to occur
2. Checks to see if the FDC is busy
3. If Busy then do result phase of READ/WRITE
4. If Not Busy do a Sense Interrupt
a. If status Register 0 Bits 7,6,5 = 001 means Seek/ReCal OK
b. If status Register 0 Bits 7,6,5 = 011 means Seek/ReCal Bad
c. If status Register 0 Bits 7,6,5 = 100 means Read/Write Bad
d. If status Register 0 Bits 7,6,5 = 110 means Drive Status Chg
e. If status Register 0 Bits 7,6,5 = 100 means Invalid Command
Then each case above is handled, followed by an additional Sense Interrupt which is supposed to result in an Invalid Command, which jumps out of the interrupt loop, does and End of Interrupt and then returns.
I read about the Invalid Command in both the 8272 and 765 spec's. But it either doesn't work this way or I'm doing something wrong.
My Cold Start Loader begins with initializing a bunch of stuff, then does a Specify, followed by a ReCal on A: then B:. The recall on A: works but it fails on B:, which never Recal's.
A little debugging, I found that after the ReCal of A: and the Sense Interrupt I found 020H in ST0. This is correct. It means bit 7,6 is normal completion, bit 5 = 1 Seek End was correct, bit 4 = 0 no equipment error, but 3 = 0 drive is READY, bit 2 =0 head 0 bit 1,0 = 00 drive A: All is good.
But after the next Sense Interrupt which is required (at least as far as I have read) causes ST0 to return 0C1H. Not Correct. It means bit 7,6 is Abnormal completion, Drive Ready Change, bit 5 = 0 Seek End was incorrect, bit 4 = 0 no equipment error, but 3 = 0 drive is READY, bit 2 =0 head 0 bit 1,0 = 01 drive B:. Yet drive B: was not even tried yet. I thought that maybe the drive polling caused this. So I checked the B: drive for ready. I saw some odd waveforms, which I want to digest some first, but don't think is a problem. I was expecting an Invalid Command not Abnormal.
I know that everything works, because my old CSL works, so it has to be my new code. So just on a flyer I changed the programming to not do a second Sense Interrupt after the RECAL. Just do the EOI and return. This works as normal. Both drives ReCal and CP/M boots and works normally.
I a little confused on how and Invalid Command can occur if a invalid command code is not issued. The second Sense Interrupt is a valid command, but there is no interrupt to sense.
I thought of timing problems, but the A: ReCal should not issue an interrupt until it is complete and no other interrupts should occur.
The Intel book states "A Sense Interrupt command must be sent after the Seek or ReCal interrupt; otherwise the FDC will consider the next command to be an Invalid Command." I agree with this and it does work this way. Then Intel furthermore states, "Also, when the last 'hidden' interrupt has been serviced, further Sense Interrupt command will result in Invalid Command Codes." I read this in two places in the Intel doc's and also in the NEC 765 doc's. Even though much of the text seems to be copied from Intel.
I want to do some more testing, but I'm still confused about the Invalid Command result from the extra Sense Interrupt. Any Ideas? Thanks Mike
My new Wait Interrupt routine
1. Waits for the interrupt to occur
2. Checks to see if the FDC is busy
3. If Busy then do result phase of READ/WRITE
4. If Not Busy do a Sense Interrupt
a. If status Register 0 Bits 7,6,5 = 001 means Seek/ReCal OK
b. If status Register 0 Bits 7,6,5 = 011 means Seek/ReCal Bad
c. If status Register 0 Bits 7,6,5 = 100 means Read/Write Bad
d. If status Register 0 Bits 7,6,5 = 110 means Drive Status Chg
e. If status Register 0 Bits 7,6,5 = 100 means Invalid Command
Then each case above is handled, followed by an additional Sense Interrupt which is supposed to result in an Invalid Command, which jumps out of the interrupt loop, does and End of Interrupt and then returns.
I read about the Invalid Command in both the 8272 and 765 spec's. But it either doesn't work this way or I'm doing something wrong.
My Cold Start Loader begins with initializing a bunch of stuff, then does a Specify, followed by a ReCal on A: then B:. The recall on A: works but it fails on B:, which never Recal's.
A little debugging, I found that after the ReCal of A: and the Sense Interrupt I found 020H in ST0. This is correct. It means bit 7,6 is normal completion, bit 5 = 1 Seek End was correct, bit 4 = 0 no equipment error, but 3 = 0 drive is READY, bit 2 =0 head 0 bit 1,0 = 00 drive A: All is good.
But after the next Sense Interrupt which is required (at least as far as I have read) causes ST0 to return 0C1H. Not Correct. It means bit 7,6 is Abnormal completion, Drive Ready Change, bit 5 = 0 Seek End was incorrect, bit 4 = 0 no equipment error, but 3 = 0 drive is READY, bit 2 =0 head 0 bit 1,0 = 01 drive B:. Yet drive B: was not even tried yet. I thought that maybe the drive polling caused this. So I checked the B: drive for ready. I saw some odd waveforms, which I want to digest some first, but don't think is a problem. I was expecting an Invalid Command not Abnormal.
I know that everything works, because my old CSL works, so it has to be my new code. So just on a flyer I changed the programming to not do a second Sense Interrupt after the RECAL. Just do the EOI and return. This works as normal. Both drives ReCal and CP/M boots and works normally.
I a little confused on how and Invalid Command can occur if a invalid command code is not issued. The second Sense Interrupt is a valid command, but there is no interrupt to sense.
I thought of timing problems, but the A: ReCal should not issue an interrupt until it is complete and no other interrupts should occur.
The Intel book states "A Sense Interrupt command must be sent after the Seek or ReCal interrupt; otherwise the FDC will consider the next command to be an Invalid Command." I agree with this and it does work this way. Then Intel furthermore states, "Also, when the last 'hidden' interrupt has been serviced, further Sense Interrupt command will result in Invalid Command Codes." I read this in two places in the Intel doc's and also in the NEC 765 doc's. Even though much of the text seems to be copied from Intel.
I want to do some more testing, but I'm still confused about the Invalid Command result from the extra Sense Interrupt. Any Ideas? Thanks Mike