Recently, my homemade 8080 CP/M 2.2 machine failed. I had some trouble with the Intel 8259 programmable interrupt controller I'm using. This prompted some additional study on the chip. I found myself interested in the difference between the buffered and non buffered mode. After a search of old books and the internet I did not find very much information. Interestingly, I found an Intel AP-31 from 1977. In this application note the buffered mode is not even mentioned. In fact, the pin 16 only has the Slave option. Intel must have changed the chip at a later date. My PIC is currently working in the non buffered mode and is performing fine. Seems the only description I can find is that the buffered mode is for 'large' systems where bus driving buffers are required on the data bus and the cascading mode is used. I have buffers on my address bus 74ls367's and use a bus controller 8238 which buffers and controls the control and data busses. Anyway I was interested enough to try it. My PIC has it's D0-7 lines connected on the buss side of the 8238 and the SP/EN tied high. I have only one PIC. So to try the buffered mode I moved the D0-7 lines to connect between the 8080 and the 8238, otherwise the bus enable would cut the data buss off from the CPU. I also connected the SP/EN to the BUS ENABLE line, pin 22 with the necessary gates. Then I wrote a short test program and tried it out, it would not work. What I think is the problem is that the 8238 is cutting off the INTA signal when the SP/EN line becomes active. So, I could trap the INTA off the CPU data buss with a status strobe, but it seems to be a lot of trouble. I do not believe that there should be any memory contention in that the PIC 'CALL instruction' is read with the INTA pulses. So... what is the buffered mode of the 8259 really for? It must have something to do with the cascade mode when more than one PIC is being used? I'm thinking that the non buffered mode on the PIC is just fine for me. Thanks Mike
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